Design
Architecture → RTL → Physical Layout → Sign-off
Architecture & RTL
D1
Chip Architecture & Microarchitecture
Define ISA, block partitioning, memory hierarchy, interconnect topology, and power/performance trade-offs. Output: architecture specification documents.
D2
RTL Design & Functional Verification
Write synthesisable RTL (Verilog / VHDL / SystemVerilog). Simulate and formally verify logic correctness with UVM testbenches and emulation platforms.
Synthesis & Physical Design
D3
Logic Synthesis & Technology Mapping
Compile RTL to gate-level netlist using a standard-cell library from the target foundry. Optimise for timing, area, and power.
D4
Place & Route (Physical Design)
Floorplan, place standard cells, route metal layers, close timing and IR-drop. Generates GDSII / OASIS layout — the blueprint sent to mask house.
Sign-off & Tape-out
D5
DRC / LVS / Timing Sign-off & Tape-out
Design-Rule Check, Layout vs Schematic, parasitic extraction, and final timing/power sign-off. Tape-out: frozen GDSII sent to mask production.
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W
Wafer Production
Silicon purification (Siemens process), Czochralski ingot growth, wire-saw slicing, lapping, etching, and CMP polishing to a mirror-finish 300 mm wafer.
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Mask Production
Photomasks → Writing Tools → Subsystems → Inspection & Repair
Mask Blank & Set Production
M1
Photomask Production
Pattern GDSII data onto quartz blanks coated with chrome or EUV absorber. Mount pellicles (thin membranes) to protect the mask surface from particles during exposure.
Mask Writing
M2
Mask Writing Tools
Multi-beam or single-beam e-beam writers expose resist on the mask blank with sub-nm placement accuracy. Write times can exceed 10 hours per mask layer.
M3
Mask Writing Subsystems
High-precision laser interferometer stages, e-beam optics columns, and high-voltage beam sources that enable mask writers to achieve their accuracy targets.
Mask Qualification
M4
Mask Inspection & Repair
E-beam or actinic (EUV-wavelength) inspection scans every mask for phase defects, particles, and CD errors. Focused ion beam (FIB) systems repair any defects found.
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Lithography Loop
⟳ Repeated 50–100+ times
one full pass per metal, poly, or oxide layer
Layer Build-up
A
Thin Film Deposition
Grow or deposit conductive (W, Cu, TiN), insulating (SiO₂, low-k), or semiconducting (poly-Si) films via CVD, PVD, or atomic-layer deposition (ALD). Each pass adds one functional layer to the growing 3-D stack.
B
Photoresist Coating & Bake
Spin-coat a chemically amplified resist (CAR) at ~30 nm thickness. Post-apply bake drives off solvent and prepares the resist film for lithographic exposure.
C
Lithography (DUV / EUV Exposure)
Project the photomask pattern onto the resist using 193 nm immersion (DUV) or 13.5 nm (EUV) light. A single TWINSCAN NXE EUV scanner costs ~$380M and weighs 180 tonnes. Overlay accuracy must be held below 1 nm.
D
Develop & Etch
Developer dissolves exposed resist to reveal the pattern. Plasma (dry) etch then transfers the pattern into the underlying film with selectivity >20:1 to stop on the layer below. Wet strip removes residual resist.
E
Ion Implantation
Accelerate dopant ions (boron, phosphorus, arsenic, indium) into selected silicon regions to define N-type and P-type source/drain and well regions. Dose and energy are controlled to ±0.1%.
F
Metrology & In-line Inspection
CD-SEM and OCD scatterometry measure critical dimensions to ±0.1 nm. Bright-field and e-beam inspection find particles and pattern defects. Process corrections are fed back in real time via APC.
G
CMP — Chemical Mechanical Planarization
Slurry-based polishing restores the wafer surface to <1 nm global planarity before the next deposition cycle. Endpoint detection stops the polish at the correct layer to prevent over-polishing.
⟳
↩ Return to Step A — Thin Film Deposition for the next layer ·
Repeat 50–100+ times · Each iteration builds one metal, poly, or dielectric layer of the chip stack
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Packaging
Dicing → Assembly → Advanced Integration → Test & Burn-in
Wafer-Level Preparation
P1
Wafer Probe & Electrical Sort
Automated probe cards contact every die on the wafer and run structural and functional tests. Failing dies are inked or mapped; only known-good dies proceed to assembly.
P2
Wafer Backgrind & Dicing
Grind wafer backside to target thickness (50–775 µm). Laser or blade dicing then singulates individual dies from the wafer. Stealth dicing minimises chipping at advanced nodes.
Die Assembly
P3
Die Attach & Interconnect
Attach die to substrate (wire bond, flip-chip C4 bumps, or micro-bumps for 2.5D/3D stacking). Underfill epoxy is dispensed to relieve thermal stress between die and package.
Advanced Packaging
P4
Advanced Packaging (2.5D / 3D Integration)
CoWoS (Chip-on-Wafer-on-Substrate) and SoIC stack HBM memory or chiplets with TSVs and hybrid bonding. Enables bandwidth >1 TB/s between stacked dies — critical for AI accelerators.
Encapsulation & Final Test
P5
Moulding, Marking & Final Test
Epoxy mould compound encapsulates the die. Laser marking adds part number / lot ID. Final ATE test (structural, functional, at-speed) and burn-in screen for infant mortality defects.
Design (EDA + Tape-out)
$50M–$500M+
Leading-edge SoC design cost
Mask Set
$5M–$50M
Per full-reticle EUV mask set
Fab Equipment
$10B–$25B+
All manufacturing tools combined
Fab Construction
$5B–$15B
Cleanroom, power, water, infra
Total Leading-Edge Fab
$15B–$40B+
3–5 nm class full build-out
Loop Iterations
50–100+
Layer cycles per wafer